In the realm of semiconductor packaging technology, a quiet revolution is unfolding. As demand for artificial intelligence (AI) chips surges, traditional packaging technologies are struggling to keep up. TSMC and Samsung Electronics, two titans of chip manufacturing, are exploring a new packaging technology—Panel-Level Packaging (PLP)—to break through the existing capacity bottleneck.

Panel-Level Packaging: A New Hope for AI Chip Capacity

Panel-Level Packaging technology, especially Fan-Out Panel-Level Packaging (FO-PLP), is seen as the key to boosting AI chip production. Compared to traditional Fan-Out Wafer-Level Packaging (FOWLP), FO-PLP uses larger square substrates with an area utilization rate of over 95%, significantly increasing packaging efficiency.

TSMC is currently testing a rectangular substrate measuring 510mm by 515mm, which has more than four times the usable area of a traditional 12-inch circular wafer. This technological transformation is expected to significantly increase the output of AI chips, easing the pressure on the capacity of the current CoWoS (Chip on Wafer on Substrate) packaging technology.

Samsung: Early Explorer

However, in this race for packaging technology, Samsung Electronics appears to have taken the lead. As early as 2015, Samsung began advancing the development of FO-PLP technology and completed a strategic acquisition of the PLP business in 2019. The Tensor G2 chip in Google's Pixel 7 series, manufactured based on Samsung's 5nm process node, was packaged using FO-PLP technology for the first time in a mobile SoC, indicating that Samsung has had the mass production capability of FO-PLP since 2023.

Challenges and Opportunities of Panel-Level Packaging

Despite the obvious advantages of FO-PLP technology, it also faces several challenges in practical application. The first is the standardization of substrate materials and sizes, as well as the limitations of line width technical specifications. These technical difficulties require further innovation and breakthroughs to meet the design needs of high-performance chips.

Furthermore, the promotion of FO-PLP technology also requires the collaborative efforts of the entire industry chain, including material suppliers, equipment manufacturers, and packaging and testing companies. Only through the joint efforts of the entire industry can FO-PLP technology achieve large-scale production, reduce costs, and increase capacity.

Layout of Domestic and Foreign Manufacturers

In addition to TSMC and Samsung, many domestic and foreign manufacturers are actively deploying FO-PLP technology. For example, South Korea's Nepes has achieved mass production of a 600mm by 600mm square panel solution, and domestic companies such as FUTIAN FENG Microelectronics and YICHENG Technology are also researching and developing related technologies. In addition, panel manufacturers such as Innolux are also activating old production lines by converting them to high-value FOPLP semiconductor packaging production lines.

Conclusion

Panel-Level Packaging technology, especially FO-PLP, offers new possibilities for increasing the production capacity of AI chips. Although there are still technical challenges and issues of industrial collaboration, with the continuous maturation of technology and the expansion of the market, FO-PLP is expected to become another powerful force in the advanced packaging market. For chip manufacturers like TSMC and Samsung, whoever can make a breakthrough in this field may gain the upper hand in the future semiconductor competition.

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